1. Field of the Invention
This invention relates to a method of fabricating an integrated circuit, and more particularly, to a method for defining a small pitch.
2. Background of the Invention
Integrated circuits are commonly used in a variety of electronic devices, especially miniature electronic devices. While modern integrated circuits may have high device densities up to millions of devices per single chip, many applications require even higher densities. Thus, circuit designers often try to increase the level of integration or density of features within an integrated circuit by reducing the size of the individual features and by reducing the pitch (i.e., the center-to-center distance between two neighboring features) on an integrated circuit. Lithography is a manufacturing process that may achieve the objectives of higher density and smaller size. However, the lithography resolution may be limited by various factors, such as the equipment, the wavelength of light sources, and the type of masks used. Several resolutions have been proposed to obtain a small pitch in an integrated circuit that may be beyond the lithographic resolution currently available.
U.S. Pat. No. 7,183,205 to Hong proposed a method that can reduce the pitch in a device below what was producible by the lithographic process. Referring to FIGS. 1(a)-1(g), the method proposed includes a thermal oxidation process on a structure as in FIG. 1(a) to form the structure of FIG. 1(b). During the thermal oxidation, the polysilicon features 105 in FIG. 1(a) will shrink vertically and horizontally to develop into the features 106 in FIG. 1(b). An etching process is then performed to expose portions of substrate 101 as shown in FIG. 1(c). Following the etching process, a layer of silicon oxide 115 is deposited on the structure of FIG. 1(c) by high density plasma chemical vapor deposition (CVD) to form a structure as in FIG. 1(d). The CVD process is followed by a chemical mechanical planarization (CMP) to remove the layer 115 to the level to the top surface of the features 106 as shown in FIG. 1(e). The features 106 are removed by a plasma process as in FIG. 1(f). A final etching process is performed and results in the structure of FIG. 1(g) where the width 117 is narrower than the original width of the features 105 and the pitch is reduced.
U.S. Patent Publication No. 2007/0051982 proposed fabrication methods for obtaining a reduced pitch less than 2 F. With an initial structure as shown in FIG. 2(a) having a polysilicon layer 54 on top of an ONO layer 55 which is over a substrate 42, and a patterned nitride layer with features 60 over the polysilicon layer 54, the process starts with a SiN liner deposition to form a structure as in FIG. 2(b). Referring to FIG. 2(c), polysilicon is then deposited to fill in the spacer 61′ between the two neighboring liners 62 which may be followed by a CMP process. After that, an etching process is performed to remove the liner 62 and nitride features 60 and leave the filled-in polysilicon 64 as shown in FIG. 2(d). As shown in FIG. 2(e), another liner 72 is deposited over the structure as in FIG. 2(d). An etching process and a second polysilicon deposition are performed which results in a structure as in FIG. 2(f). Referring to FIGS. 2(g) and 2(h), the liner 72 is then removed by a wet etching process, which is followed by a hard mask etching process to remove the polysilicon layer 54.